1. Field of the Invention
The present invention relates to a MPEG video decoding system, and more particularly, to a MPEG video which is capable of supporting a digital video format.
2. Discussion of the Related Art
FIG. 1 is a block diagram of a general Moving Picture Experts Group-2 (MPEG-2) video decoding system. Referring to FIG. 1, the MPEG system decoding system includes an MPEG system decoder 101, a video decoder 102, a video display processor (VDP) 103, an audio decoder 104, a memory interface 105, and a host interface 106. Further, an external DRAM memory is connected to the memory interface 105. The external DRAM memory stores input bitstreams and frame-buffers for motion compensation. In order to support an MP@HL mode in MPEG-2 standard as shown in FIG. 1, bit-buffer size of about 10 Mbits is required and a maximum allowable bit rate reaches about 80 Mbit/s.
Meanwhile, digital TVs (DTVs) employing the MPEG video decoding system of FIG. 1 support a variety of functions, mainly a picture in picture (PIP) function till now. The DTVs are limited in a form of DTV+NTSC or DTV+PC external input.
Recently, a high-end DTV is equipped with an IEEE-1394 interface unit and there is a tendency to manufacture a product that transmits/receives data at a high speed. As an example of application products, a product connected to a digital camcorder through IEEE-1394 is available. The product improves a degradation of a picture quality, which is caused when a general TV and a digital camcorder are connected to each other through a conventional analog interface. Therefore, the product can obtain a good picture quality because data is transmitted/received between the DTV and the digital camcorder in a digital format.
A conventional high-end DTV must use chips that are configured with an IEEE-1394 transceiver, a format decoder for digital video (DV) format as a standard format recorded in a digital camcorder, and an MPEG-2 video decoder. In other words, since a conventional video decoding chip includes the MPEG-2 video decoder and the DV decoder for the MPEG video and the DV format, gate size, memory and chip cost are increased, resulting in an increase of cost.
Accordingly, there is a demand for a development of an efficient video decoding chip which is capable of supporting both the high definition (HD) video signal decoder and the DV format decoder, considering a limitation of memory, chip size and bandwidth of data bus.